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CXD1176Q
8-bit 20MSPS Video A/D Converter with Clamp Function
Description The CXD1176Q is an 8-bit CMOS A/D converter for video use that features a sync clamp function. The adoption of a 2 step-parallel method realizes low power consumption and a maximum conversion speed of 20MSPS. Features * Resolution power: 8-bit 1/2LSB (DL) * Maximum sampling frequency: 20MSPS * Low power consumption: 60mW (at 20MSPS typ.) (Reference current excluded) * Built-in sync type clamp function * Built-in monostable multivibrator for clamp pulse * * * * * * * * * generation Built-in sync pulse polarity selection function Clamp pulse direct input possible Built-in clamp ON/OFF function Built-in reference voltage self-bias circuit Input CMOS compatible 3-state TTL compatible output Single 5 V power supply Low input capacity: 11 pF Reference impedance: 330 (typ.) 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD 7 * Reference voltage VRT, VRB VDD + 0.5 to VSS - 0.5 * Input voltage VIN VDD + 0.5 to VSS - 0.5 (Analog) * Input voltage VI VDD + 0.5 to VSS - 0.5 (Digital) * Output voltage VO (Digital) * Storage temperature Tstg
V V V V
VDD + 0.5 to VSS - 0.5 V
-55 to +150
C
Applications TV and VCR digital systems and a wide range of applications where high-speed A/D conversion is required. Structure Silicon gate CMOS IC
Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS | DVSS - AVSS | 0 to 100 mV * Reference input voltage VRB 0 to V VRT to 2.7 V * Analog input VIN 1.8Vp-p above * Clock pulse width Tpw1, Tpw0 22.5 ns (min) to 1.1 s (max) * Operating ambient temperature Topr -40 to +85 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E90167J04-TE
CXD1176Q
Block Diagram and Pin Configuration
DVss 28 OE 30 Reference supply DVss 31 24 VRB D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) 1 23 AVss 2 3 4 5 6 7 8 16 AVDD DVDD 10 DVDD 11 CLK 12 Clock generator Upper data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) Lower data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) 22 AVss 21 VIN 20 AVDD 19 AVDD 18 VRT 17 VRTS 25 VRBS
Upper encoder (4 BIT)
Upper sampling comparator (4 BIT)
NC
9
15 PW 14 Sync M*M 29 CLE 27 CCP 26 VREF 13 SEL
NC 32
--2--
CXD1176Q
Pin Description Pin No. Symbol Equivalent circuit Description
Di
1 to 8
D0 to D7
D0 (LSB) to D7 (MSB) output
9, 32 10, 11
NC DVDD
NC pin Digital +5 V
DVDD
12
CLK
12
Clock input
DVSS
DVDD
13
SEL
13
DVSS
When SEL is at low, with the falling edge of Pin 14 (sync) as trigger, the monostable multivibrator generates clamp pulses. When SEL is at high, with the rising edge of Pin 14 (sync) as trigger, it generates clamp pulses.
DVDD
14
Sync
14
Trigger pulse input to the monostable multivibrator. Trigger polarity can be selected through Pin 13 (SEL).
DVSS
--3--
CXD1176Q
Pin No.
Symbol
Equivalent circuit
Description
DVDD
15
PW
15
DVSS
When a clamp pulse is generated at the monostable multivibrator, the pulse width is determined by the external R and C. When the clamp pulse is directly input, it is input to Pin 15 (PW). The signal voltage of the low period is clamped. (Here, Pin 14 (sync) is fixed to either low or high.) Analog +5 V
AVDD
16, 19, 20
AVDD
17
VRTS
17
When shorted with VRT, generates approx. +2.6 V.
18
VRT
AVDD
Reference voltage (top)
18
24
24
VRB
AVSS
Reference voltage (bottom)
AVDD
21
VIN
21
Analog input
AVSS
22, 23
AVSS
AVSS
Analog ground
25
VRBS
25
When shorted with VRB, generates approx. +0.5 V.
--4--
CXD1176Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
26
VREF
26
Clamp reference voltage input. Clamps to provide a clamp period input signal equal to the reference voltage.
AVSS
AVDD
27
CCP
27
Integrates the voltage for clamp control. CCP and VIN voltage changes are in positive phase.
AVSS
28, 31
DVSS
Digital ground.
DVDD
29
CLE
29
DVSS
CLAMP PULSE
When CLE is at low, clamp function is activated. When CLE is at high, clamp function is OFF and only the usual A/D converter function is active. By connecting CLE pin to DVDD via a several hundred resistance, the clamp pulse can be tested.
DVDD
30
OE
30
When OE is at low, Data is output. When OE ia at high, D0 to D7 pins turn to high impedance.
DVSS
--5--
CXD1176Q
Digital Output Correspondence between the analog input voltage and the digital output code is indicated in the chart below.
Input signal voltage VRT . . . . . . . . . . . . VRB
Step 0 . . . 127 128 . . . 255
Digital output code MSB LSB 1 1 1 1.1 . . 10000 0 1 1 1.1 . . 00000 111 000 111 000
TPW1
TPW0
Clock
Analog input
N
N+1
N+2 N-1
N+3
N+4
Data output
N-3
N-2
N
N+1
Td = 18ns : Points where analog signals are sampled.
Timing Chart. I
tr = 4.5ns
tf = 4.5ns 90% 5V
OE input
2.5V tPLZ 10% tPZL 0V VOH
Output 1 10% tPHZ 90% Output 2 tPZH
1.3V VOL ( DVSS) VOH ( DVDD) 1.3V VOL
Timing Chart. II
--6--
CXD1176Q
Electrical Characteristics Analog characteristics Item Symbol (Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 C) Conditions VDD = 4.75 to 5.25 V Ta = -40 to +85 C VIN = 0.5 to 2.5 V fIN = 1 kHz ramp Envelope Potential difference to VRT Potential difference to VRB End point NTSC 40 IRE mod ramp Fc = 14.3 MSPS -60 +20 Min. Typ. Max. Unit
Conversion speed
Fc
0.5
20
MSPS
Analog input band width (-1dB) Offset voltage1 Integral non-linearity error
BW EOT EOB EL
18 -40 +40 +0.5 0.3 1.0 0.5 30 4 -20 +60 +1.3 0.5
MHz mV
LSB % deg ps ns
Differential non-linearity error ED Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage2 Clamp pulse width (Sync pin input) Clamp pulse delay DG DP
taj tsd
Eoc VIN = DC, PWS = 3 s VREF = 0.5 V VREF = 2.5 V 0 -50 1.75
+20 -30 2.75 25
+40 -10 3.75
mV s ns
tcpw tcpd
C = 100 pF, R = 130 k (15 PIN)
1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001". EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from "11111111" to "11111110". 2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be generated.
--7--
CXD1176Q
DC characteristics Item Supply current Reference pin current Analog input capacitance Reference resistance (VRT to VRB) Self-bias I Self-bias II Digital input voltage IDD IREF CIN RREF VRB1
(Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 C) Conditions Fc = 20 MSPS NTSC ramp wave input 4.5 VIN = 1.5 V + 0.07 Vrms 230 0.48 1.96 Min. Typ. 12 6.6 11 300 0.52 2.08 2.32 4.0 1.0 5 5 450 0.56 2.22 Max. 18 8.7 Unit mA mA pF V V V
VRB and VRBS are shorted VRT1 to VRB1 VRT and VRTS are shorted VRT2 VIH VIL IIH IIL IOH VRB = AGND VRT and VRTS are shorted VDD = 4.75 to 5.25 V Ta = -40 to +85 C VIH = VDD VDD = max OE = VSS VDD = min OE = VDD VDD = max VIL = 0V
Digital input current
A
VOH = VDD - 0.5 V -1.1 VOL = 0.4V VOH = VDD VOL = 0V 3.7 16 16
mA
Digital output current
IOL IOZH IOZL
A
Timing Item Output data delay Tri-state output enable time Tri-state output disable time
(Fc = 20 MSPS, VDD = 4.75 to 5.25 V, VRB = 0.5 V, VRT = 2.5 V, Ta = -40 to +85 C) Symbol TDL Conditions with TTL 1 gate and 10pF load RL = 1k, CL = 20 pF OE = 3 V 0 V RL = 1 k, CL = 20 pF OE = 0 V 3 V 2.5 8 Min. Typ. 18 6 18 Max. 30 10 30 Unit ns ns ns
tPZH tPZL tPHZ tPLZ
--8--
CXD1176Q
Electrical Characteristics Measurement Circuit Integral non-linearity error Differential non-linearity error Offset voltage
+V Measurement point S2 S1: ON IF A < B S2: ON IF B > A S1 To output pin -V AB COMPARATOR A8 B8 to to A1 B1 A0 B0 CL 8 BUFFER RL RL DVDD
}
Tri-state output measurement circuit measurement circuit
VIN
DUT CXD1176Q
8
DVM CLK (20MHz)
"0"
"1" 8 000 * * * 00 to 111 * * * 10 Note) CL includes capacitance of the probe and others.
CONTROLLER
Maximum operational speed Differential gain error Differential phase error
}
measurement circuit
2.5V Fc - 1kHz
ERROR RATE CX20202A-1
S.G.
0.5V
H.P.F 1 2 VECTOR SCOPE
COUNTER
1 AMP
100
VIN CXD 1176Q
2.5V
8
TTL ECL
8 620 -5.2V
10bit D/A
2
40 IRE MODULATION BURST
NTSC
IAE
SIGNAL SOURCE
CLK
0 -40 0.5V SYNC
620 TTL -5.2V
D.G D.P.
S.G. (CW)
FC
ECL
Digital output current measurement circuit
2.5V 0.5V
VDD VRT VIN VRB CLK OE GND VOL
IOL
2.5V 0.5V + -
VDD VRT VIN VRB CLK OE GND VOH
IOH
+ -
--9--
CXD1176Q
Vi (1)
Vi (2)
Vi (3)
Vi (4)
Analog input
External clock
Upper comparators block
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
Upper data
MD (0)
MD (1)
MD (2)
MD (3)
Lower reference voltage
RV (0)
RV (1)
RV (2)
RV (3)
Lower comparators A block
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
Lower data A
LD (-1)
LD (1)
Lower comparators B block
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
Lower data B
LD (-2)
LD (0)
LD (2)
Digital output
Out (-2)
Out (-1)
Out (0)
Out (1)
Timing Chart 3 Operation (See Block Diagram and Timing Chart 3) 1. The CXD1176Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT - VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom). --10--
CXD1176Q
2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1 F set as close as possible to the pin to bypass to the respective GND's. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100 in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1 F, stable characteristics are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6 V and VRB = 0.6 V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18 ns. 6. OE pin By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained. 7. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
--11--
CXD1176Q
Application Circuit (1) Case where clamp pulse is directly input (self-bias used)
HCO4 CLOCK IN CLAMP PULSE IN LATCH CK Q 0.01 +5V (Analog) 17 18 19 VIDEO IN 10 75 0.1 10P 20 21 22 23 0.01 +5V (Analog) VREF 20k GND (Analog) 24 25 26 27 28 0.01 GND (Digital) 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0
+5V (Digital) 0.1
(2) Example where pedestal clamp is executed by sync pulse (self-bias used)
+5V (Digital) HCO4 CLOCK IN SYNC IN LATCH CKQ 0.01 +5V (Analog) 17 18 19 VIDEO IN 10 75 0.1 10P 20 21 22 23 0.01 +5V (Analog) VREF 20k GND (Analog) 24 25 26 27 28 0.01 GND (Digital) 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1
The clamp pulse is latched by the ADC sampling clock, but that is not necessary for clamp basic operation. However, slight beat may be generated as vertical sag according to the relation between the sampling frequency and clamp pulse frequency. At such time, the latch circuit is effective. (See page 20 Notes on Operation 5.) --12--
CXD1176Q
(3) Digital clamp (self-bias used)
+5V (Digital) HCO4 CLOCK IN CLAMP PULSE IN 17 18 19 VIDEO IN 10 75 0.1 10P 0.01 22 23 24 25 26 27 28 29 30 31 32 DAC, PWM, etc. GND (Digital) GND (Analog) 20 21 OPEN 8 7 6 5 4 3 2 1 Latch, Subtracter, Comparator, etc. Clamp Level setting data 0.1
16 0.01 +5V (Analog)
15
14
13
12
11
10
9
(4) When clamp is not used (self-bias used)
+5V (Digital) HCO4 CLOCK IN 16 0.01 +5V (Analog) 17 18 19 VIDEO IN 75 0.1 10P 0.01 22 23 24 25 26 27 28 29 30 31 32 20 21 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1
+5V (Digital) GND (Analog)
GND (Digital)
--13--
CXD1176Q
8-bit 20MSPS ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD1176Q (8bit 20MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation board is composed of a main board common to either type, to which is added sub board CXD1176Q or sub board CXD1171M. The junction is made through a socket. To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is mounted CXD1176Q and CXD1171M respectively. Those IC's are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram
VOUT
ANALOG CIRCUIT MOUNT PORTION
DAC SOCKET
8
V REF
VIN
ANALOG INPUT INTERFACE
ADC SOCKET
8
4 CLOCK BUFFER
DATA LATCH
DIGITAL CIRCUIT MOUNT PORTION
ANALOG CIRCUIT MOUNT PORTION
OSC
SW
GND +5V
-5V
CLOCK OE
SEL SYNC CLE Unnecessary at self-bias use
BLK
Characteristics * Resolution * Maximum conversion rate * Digital input level * Supply voltage Supply voltage Item +5 V -5 V Clock input CMOS compatible Pulse width TCW1 TCW0 Min.
8 bit 20 MHz CMOS level 5.0 V (Single +5 V power supply possible at self bias use)
Typ.
Max. 150 20
Unit mA
22.5 ns (min) 22.5 ns (min) --14--
CXD1176Q
Analog Output (CXD1171M) Item Analog output Min. 1.9 Typ. 2.0
(RL > 10 k) Max. 2.1 Unit V
Output Format (CXD1176Q) The table shows the output format of AD Converter. Analog input voltage VRT . . . . . . . . . . . . VRB Step 0 . . . 127 128 . . . 255 Digital output code MSB LSB 1 1 1 1.1 . . 10000 0 1 1 1.1 . . 00000 111 000 111 000
Timing Chart
Analog input
External clock
Tpw0 Tpw1 Tdc tPD (AD)
AD clock
AD output tDD Latch output DA input ts DA clock th
DA output
tPD (DA)
Item Clock High time Clock Low time Clock Delay Data delay AD Data delay (latch) Set up time Hold time Data delay DA
Symbol TPW1 TPW0 Tdc
Min. 25 25
Typ.
Max.
Unit ns ns
24 18 30 5 5 10 10 --15--
ns ns ns ns ns ns
tPD (AD) tDD tS th tPD (DA)
CMOS ADC/DAC Peripheral Circuit Board (Main Board)
DVDD DVSS
13 NC 0.01 CLK 9 8 7 6 5 4 3 2 1 0.01 CLK 9 8 7 6 5 4 3 2 16 74S174 (LATCH) 0.01 1 8 9 10 11 12 13 DVDD 47 0.01 DVDD DVSS 14 7 6 5 4 3 2 1 BLK OE SEL CLE OSC SWITCH EXT/INT SYNC R9 75 DVSS 1 CLEAR OSC out 0.01 DVDD 14 DVSS 15 DVDD 7 8 10 SYNC 14 SEL 13 CLK 12 DVDD 11 14 D7 10 D6 9 D5 8 D4 7 D3 6 D2 5 D1 4 D0 3 DVSS 2 OE 1 13 12 11 SW1 15 PW 16 NC SW2 18 VRT C3 0.01 20 AVDD 21 AVDD 22 VIN 23 AVSS C4 0.01 25 VRBS 26 VRB 27 VREF 28 CLE 24 AVSS 19 VRTS 17 NC DVSS CLEAR 74S174 (LATCH) 10 11 12 13 14 15 DVDD 16 DVSS 14 NC 15 AVSS R8 3.3k (16R) 18 VREF D6 7 D5 6 D4 5 D3 4 D2 3 D1 2 D0 1 19 AVDD R7 200 (R) 22 IO 23 NC 24 DVDD V out 21 IO 20 AVDD 17 IREF D7 8 16 AVSS BLK 9 CLK 10 DVSS 11
OUTPUT GAIN ADJUST VR4 20k NC 12 C5 0.1
VRB ADJUST
VRT ADJUST
AVDD
R4 510
VR1 2k
VR2 2k Q1
Q2
R6 510
R5 510
AVSS
74S04 OR 74HC04 (INV BUFFER)
-5V +5V GND AVDD DVDD
--16--
VR3 20k SW3 47
VIDEO INPUT
AVDD
Q3
C2 R3 10 33
R1 100k
C1 470
R2 75
AVSS
CLAMP VOLTAGE ADJUST
EXTERNAL CLOCK INPUT
(RIN = 75) SYNC INT 47
CXD1176Q
VR5 20k
R10 75
CXD1176Q
CMOS ADC/DAC Peripheral Circuit Board (Sub Board)
PW 15 NC 16 NC 17 VRTS 18 VRT 19 AVDD 20 AVDD 21 VIN 22 AVSS 23 AVSS 24 VRB 25 VRBS 26 VREF 27 CLE 28 C1 0.01 C5 C3 0.1 17 18 19 20 CXD1176Q 21 22 23 24 25 26 27 28 29 30 31 32 4 3 2 1 C2 0.1 16 15 14 13 12 11 10 9 8 7 6 5
14 SYNC 13 SEL 12 CLK 11 DVDD
10 D7 9 8 7 6 5 4 3 2 1 D6 D5 D4 D3 D2 D1 D0 DVSS OE
NC 13 NC 14 AVSS 15 AVSS 16 IREF 17 VREF 18 AVDD 19 AVDD 20 IO 21 IO 22 NC 23 DVDD 24 C3 C2
13 14 15 16 17 18 CXD1171M 19 20 21 22 23 24
12 11 10 9 8 7 6 5 4 3 2 1 C4
12 NC 11 DVSS 10 9 8 7 6 5 4 3 2 1 CLK BLK D7 D6 D5 D4 D3 D2 D1 D0
C1
--17--
CXD1176Q
List of Parts
resistance R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 VR1 VR2 VR3 VR4 VR5 100 k 75 75 510 510 510 R = 200 18R 3.3 k 75 75 2 k 2 k 20 k 20 k 20 k transistor Q1 2SC2785 Q2 2SC2785 Q3 2SC2785 IC IC1 IC2 IC3 oscillator OSC others connector BNC071 SW AT1D2M3
74S174 74S174 74S04
capacitance C1 470 F/6.3 V (chemical) C2 10 F/16 V (chemical) C3 0.01 F C4 0.01 F C5 0.1 F C6 0.1 F C7 0.1 F C8 0.1 F C9 0.1 F C10 0.1 F C11 47 F/10 V (chemical) C12 47 F/10 V (chemical) C13 47 F/10 V (chemical) C14 0.1 F
Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When self-bias is used, there is no need for adjustment. Reference voltage is set through self-bias delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full-scale adjustment (VR4) Full-scale voltage of D/A converter output is adjusted at the PCB shipment, the full-scale voltage is adjusted to approx. 2 V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5 V to an H sync of 0 to 5 V.
--18--
CXD1176Q
5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: OE, SEL, Sync, CLE, Sync INT (CXD1176Q) and BLK (CXD1171M). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a horizontal synchronizing signal above 3.5 Vp-p Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync and Sync INT pin. At the PCB shipment the main board pins are set as follows. * OE ... Low (A/D output ON) * SEL ... Low (Pulse generated with Sync falling edge as trigger) * Sync ... Line junction with Sync INT pin * CLE ... Low (Clamp function ON) * BLK ... Low (Blanking OFF) 6. Clamp pulse input method One method, as shown in Application Circuit examples (1) and (2), is to directly input the clamp pulse. The other is to use the built-in monostable multivibrator. The method is selected through SW1. At the PCB shipment it is set to direct input. To use the built-in monostable multivibrator, it is necessary to mount on the CXD1176Q sub board, R and C that determine pulse width. (Ex. R = 130 k, C = 100 p, Tpw = 2.75 s Typ.)
Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, See p. 23 Component side diagram.) 2. At CXD1176Q sub board, C2 and C3 capacitors serve the important role of bringing out CXD1176Q's full performance. There are over 0.1 F (ceramic) capacitors with good high frequency characteristics. Layout as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage and power source. Keeping ADC's DVSS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout where ADC is close to the voltage supply source, is recommended. (For 2, see p. 23 Component side diagram.) 4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not have any jitter. 5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage generating source. On this PCB, the layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems.
--19--
CXD1176Q
Notes on Operation 1. Reference voltage Shorting VRT and VRTS, VRB and VRBS will activate the self-bias function that generates VRT = 2.6 V and VRB = 0.5 V. On the PCB, either self-bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in selfbias. Also, to provide external reference voltage, adjust the dynamic range (VRT - VRB) to above 1.8 Vp-p. 2. Clock input There are 2 modes for the PCB clock input 1) Provided from the external signal generator. (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch IC's (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on the main board and DC voltage on the ADC side of C2 turns to about 1/2 (VRT + VRB). To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to either PW pin or Sync pin. This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling clock around ADC. If there are no problems with Vsag, latch is not necessary. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. There are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis and the mount jack.
--20--
CXD1176Q
Latch Up Prevention The CXD1176Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 16, 19 and 20) and DVDD (Pin 10 and 11), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
16
19 AVDD
20
10
11 DVDD C14 DIGITAL IC
+5V
+5V C6 CXD1176Q
AVSS 22 23 AVSS DVSS
DVSS 28 31
b. When analog and digital supplies are from a common source (i)
DVDD
16
19 AVDD
20
10
11 DVDD C14 DIGITAL IC
+5V C6 CXD1176Q
AVSS 22 23 AVSS DVSS
DVSS 28 31
(ii)
DVDD
16
19 AVDD
20
10
11 DVDD C14 DIGITAL IC
+5V C6 CXD1176Q
AVSS 22 23 AVSS DVSS
DVSS 28 31
--21--
CXD1176Q
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 16 19 AVDD +5V +5V C6 CXD1176Q DIGITAL IC 20 10 11 DVDD
AVSS 22 23 AVSS DVSS
DVSS 28 31
b. When analog and digital supplies are from a common source (i)
DVDD AVDD 16 19 AVDD +5V C6 CXD1176Q DIGITAL IC 20 10 11 DVDD
AVSS 22 23 AVSS DVSS
DVSS 28 31
(ii)
DVDD AVDD 16 19 20 AVDD +5V CXD1176Q DIGITAL IC 10 11
DVDD
AVSS 22 23 AVSS DVSS
DVSS 28 31
--22--
CXD1176Q
Silk Side
Component Side
Soldering Side (Diagram seen from the component side)
--23--
CXD1176Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
--24--
0.50
(8.0)
CXD1176Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15 0.1
25
16
A
32
9
+ 0.2 0.1 - 0.1
1 0.8 b
8 0.24 M 0 to 10
+ 0.15 b = 0.30 - 0.10 ( 0.30)
+ 0.10 0.127 - 0.05
b = 0.30 0.03
(0.127)
DETAIL A : SOLDER
DETAIL A : PALLADIUM
PACKAGE MATERIAL EPOXY RESIN SOLDER / PALLADIUM PLATING 42 / COPPER ALLOY 0.2g
SONY CODE EIAJ CODE JEDEC CODE
QFP-32P-L01 QFP032-P-0707
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
--25--
0.125 0.04
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
0.50
(8.0)

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